(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit memory devices on semiconductor substrates, and more particularly to an improved Read-Only-Memory (ROM) structure and method of fabrication.
(2) Description of the Prior Art
Read-Only-Memory (ROM) circuits are used to permanently store code in electronic equipment, such as computers, microprocessor systems and the likes. The code or information stored in the ROM circuit is non-volatile, but otherwise is available like the volatile information stored in dynamic random access memory (DRAM) or static random access memory (SRAM). However, the information stored in the ROM, such as micro-instructions for programs, is available the instant the electronic equipment, containing the ROM circuit, is powered up.
The code for the ROM is introduced during semiconductor processing by using a ROM code mask during one of the processing steps. Typically the array of binary code is represented by the presence or absence of a transistor at the memory cell locations. The presence or absence of the transistor can be achieved by designing the ROM code mask for patterning a diffusion, depletion, contacts or metal during ROM device processing. Typically, the patterning and thereby the coding is done at the substrate level to achieve the highest layout density while patterning at the contact and metal level is done to achieve the fastest turn around time to finished product.
Ultra Large Scale Integration (ULSI) on the semiconductor substrate has dramatically increased the device density, improving performance and reducing cost on circuits such as DRAM, SRAM, microprocessors and the likes. These same advances in technology, such as high resolution photolithographic techniques and advances in directional plasma etching, have also resulted in similar increases in cell density on ROM chips.
Although those skilled in the semiconductor industry are well aware of the benefits associated with down scaling the device feature sizes, such as improves circuit density and performance, numerous down-scaling problems do occur that can adversely affect device performance and reliability. One specific problem that occurs on the read-Only Memory (ROM) cell when the cell size is reduced and the array of ROM cells are coded using a conventional ion implantation for coding, is an increase in the electrical resistance of the bit lines with a corresponding decrease in circuit performance.
The nature of this problem is best understood by referring to the prior art that is shown in FIGS. 1 and 2. The typical ROM device consists partially of an array of memory cells, each cell comprised of a single field effect transistor (FET). The array of FETs are fabricated by forming a plurality of parallel, closely spaced conducting lines called "bit lines". They are formed for example by photoresist masking and implantation. The bit lines are formed of heavily doped regions, such as N-type dopants, in a semiconducting substrate 10 having a background or substrate doping of the opposite polarity. For example, doped with boron (B). A top view of the bit lines labelled BL1, BL2 and BL3 are shown in FIG. 1, and a cross section through the section 2--2 of FIG. 1 is shown in FIG. 2. For practical reasons, only a portion of the ROM structure is shown. The bit lines serve as the source/drain areas of the array of FETs. A thin gate oxide 12 between the bit lines and a thicker insulating oxide 14 over the bit lines, as shown in FIG. 2, are then formed on the substrate surface, for example, by thermal oxidation. A plurality of parallel, closely spaced conducting lines, called "word lines" are formed orthogonal to the bit lines over the oxide layer. The word lines are usually formed by depositing and patterning a doped polysilicon layer. Two of the plurality of word lines formed are depicted in FIG. 1 and labeled as WL1 and WL2. The portion of the word lines over the gate oxide function as the gate electrodes of the array of FETs that are now built. The word lines and bit lines are connected by a patterned metallurgy to suitable peripheral circuits (not shown) that allow the array of FETs to be electrically addressed and interrogated.
Selected FETs can now be modified to make them permanently non-conductive, thereby coding the ROM array. A ROM implant code mask composed of photoresist 16, as shown in FIG. 2, is patterned forming ROM code openings over the FET gate areas selected for coding, one opening 18 of which is shown in FIG. 1 and 2. A ROM code implant 20, such as a boron (B.sup.11) implantation, is carried out so as to program the ROM chip by forming a high concentration doped region 22. This implant increases the FET threshold voltage (V.sub.t). to a value greater than the applied gate voltage (V.sub.g). When the chip fabrication is complete, and the gate voltage V.sub.g is applied to the word line WL2 over the implanted region 22, via the address circuit, the FET in the code cell does not turn on, and thereby, represent a binary 0. However, in cells that are masked from implantation, such as the adjacent cell in region 24, as shown in FIG. 2, the low P- doped surface is inverted and the FET having a V.sub.t less than the V.sub.g turns on. This provides a conducting path between the source and drain formed from bit lines BL1 and BL2, and thereby, for example, represents a binary 1.
Unfortunately, when the code implantation is performed the transverse straggle from the implant and the thermal cycle to activate the implanted atoms in region 22 result in lateral diffusion of the dopant which causes counter-doping of the adjacent bit lines BL2 and BL3, as shown in FIG. 2. This substantially constricts the width of the buried bit line adjacent to the code implant region 22 and increases substantially the bit line resistance. The problem is further exacerbated if two adjacent memory cells are ROM coded by ion implantation.
As the bit lines are further reduced in width during down scaling, the restriction in the width of the bit lines by ROM code implantation substantially increases the resistance and further degrades circuit performance. One method of reducing this bit line resistance is described by T. D. H. Yiu, in U.S. Pat. No. 5,117,389 in which design changes form subarrays of memory cells that are selected by block select transistors and share a common metal bit line to reduce the bit line resistance. Although the circuit performance is improved, the semiconductor processing is substantially more complex.
Therefore, there is still a strong need in the semiconductor industry to minimize the resistance of the bit line without substantially increasing the process complexity.